L-NESS

Laboratory for Epitaxial Nanostructures on Silicon and Spintronics

Affiliated Institutions

Nanoscale Device Group

News

03 Aug2012Our work on graphene logic gates has been featured in NanotechWeb and PhysicsWorld
20 Mar2012We developed the first wafer-scale integrated graphene logic gates operating under ambient conditions. This work was done in collaboration with the University of Illinois Urbana-Champaign.
23 Dec2011Our work on graphene voltage amplifier has been featured in NanotechWeb
30 Aug2011We developed the first high-gain (> 10 dB) graphene voltage amplifier
05 Nov2010Our work on graphene nanoribbon memory cells has been featured in PhysicsWorld and NanotechWeb
15 Apr2010We developed the first graphene nanoribbon memory device. This work was done in collaboration with the MPI Stuttgart.
06 Jul2009Our research in the Italian press
29 Apr2009Our work on graphene integrated circuits has been featured in PhysicsWorld and NanotechWeb
05 Mar2009We developed the first graphene integrated circuit
05 Dec2008We developed the first graphene logic gates

People

Former group members

Research

Graphene nanoelectronics

Graphene, a recently isolated single sheet of graphite, is currently being investigated as a viable alternative to Si for the channel of field-effect transistors (FETs) at the sub-10 nm scale, at which the ultimate limits of Si technology would probably be reached. The high mobility of carriers in graphene could allow fabrication of FETs with a very low channel resistance, resulting in a high operational speed. The remarkable electronic properties of graphene and its compatibility with Si lithographic techniques promise to simplify the transition to carbon-based electronics. Large-scale fabrication of graphene is currently being attempted by epitaxial growth, transfer printing, deposition from a solution, or anodic bonding.

Our group is interested in the development of graphene nanoelectronic devices. We developed the first logic gates and the first integrated circuit (complementary inverter) on graphene.

A schematic of the fabricated integrated complementary graphene inverter is shown in Fig. 1. We isolated graphene on an insulating substrate by peeling graphene flakes from a piece of graphite with an adhesive tape. The same method was used to isolate graphene for the first time. We fabricated two transistors on the same graphene flake by electron beam lithography. The key to obtaining a functional integrated circuit was to change the type of one of the transistors from p to n by Joule heating. An ideal graphene transistor is n-type, meaning that electrons pass current, when a positive voltage is applied to the gate but p-type when a negative voltage is applied. Contamination from oxygen and water vapour in the air, however, causes the switchover "Dirac" point to shift from zero to a positive voltage, making the transistor p-type. We passed a large current through one transistor and the heating effect of the current removed the contaminants, shifting its Dirac point back and therefore restoring n-type behaviour. In this way we obtained two transistors of opposite type integrated on the same graphene flake. This pair of transistors forms a digital logic inverter, a basic building block of CMOS.

Fig. 1. Integrated complementary graphene inverter. (a) A schematic of the fabricated inverter. Three electrodes patterned on the same flake of monolayer graphene define two FETs. The part of the flake between the two leftmost electrodes (depicted in red) is electrically annealed to obtain an n-type FET. The other part of the flake (depicted in blue) is a p-type FET. (b) The measured DC voltage transfer characteristics of the fabricated complementary graphene inverter. Insets: SEM image of the fabricated inverter and the circuit layout.

Research on graphene has been done in collaboration (μRaman) with the Micro and nanostructured materials lab, Politecnico di Milano, Italy.

Semiconductor nanofluidic devices for nanomedicine

Biochemical reactions usually involve a large number of protein and nucleic acid molecules interacting at the nanoscale. Exploring the microscopic basis of such reactions is often obscured because averaged responses from an enormous number of individual molecules are measured in the experiment. Ability to separate, isolate, and investigate a small number of molecules in a nanoscale-confined environment is a long-sought goal of molecular diagnostics.

The affordability of a molecular diagnostic platform is commonly at odds with the nanoscale requirements of single-biomolecular studies. To overcome this constraint, we developed an alternative technology capable of producing nanofluidic channels without expensive (in terms of cost per chip) top-down nanolithography. The vertical arrays of nanochannels are fabricated from a heterostructure comprised of a substrate and several thin sacrificial layers. The heterostructure is etched deep enough to expose the lateral surface of the required number of sacrificial layers which are then selectively wet-etched laterally to form the nanochannels. The fabricated nanochannels are shown in Fig. 2.

Fig. 2. Nanofluidic channels fabricated in two different types of SiGe heterostructure. (a) A single nanochannel structure obtained by a selective side etching of a Ge sacrificial layer on a Si0.3Ge0.7 virtual substrate. The nanochannel runs perpendicular to the image and has a cross-section of 10 nm × 10 nm. (b) A structure with three nanochannels obtained by etching Si0.6Ge0.4 sacrificial layers on a Si substrate. The nanochannels have a cross-section of 130 nm × 100 nm.

The present fabrication process is compatible with standard semiconductor technology enabling simple integration with conventional electronic and fluidic devices for fast on-chip processing. The suitability of the fabricated nanochannels for nanofluidic applications is demonstrated by observing the flow of a fluorescent dye solution through the nanochannels with the help of a confocal laser scanning microscope (Fig. 3). The potential utility of the nanochannels in biologically relevant applications - e.g., size-based separation of biomolecules - is demonstrated by imaging aggregates of amyloid beta, the amyloidogenic peptide implicated in Alzheimer's disease. The size of the amyloid beta aggregate that can enter a nanochannel is found to be dependent on the channel cross-section (Fig. 3).

Fig. 3. Overlay (reflection and fluorescence) confocal images of the nanochannels. (a) A three nanochannel Si/Si0.6Ge0.4 structure in which the nanochannels are filled with fluorescent dye (green signal). (b) Labelled amyloid beta aggregates in the nanochannels. The smaller nanochannel (marked by 1) has a cross-section of 260 nm × 300 nm. The larger nanochannel (marked by 2) has a cross section of 310 nm × 300. The mostly empty nanochannel (marked by 3) has a cross section of 350 nm × 300 nm. Large aggregates are found only in the nanochannel 2, while small aggregates are visible both in nanochannels 1 and 2.

Research on nanofluidics has been done in collaboration with the Nanoscale Diagnostics Group, Max Planck Institute for Solid State Research, Germany and Department of Experimental Medicine, University of Milan - Bicocca, Italy.

Nanoelectronics in semiconductor heterostructures

The research on low-dimensional systems has mainly been focused on field effect transistors, yet many conventional applications cannot be realized without diodes. For this reason one of the nanostructures we developed was a gate-controlled rectifier. The use of gate-induced junctions opens a route to reconfigurable electronic devices and provides valuable insight into the understanding of low-dimensional nanostructures. The fabricated gate-controlled diode is shown in Fig. 4. The diode was fabricated by patterning a SiGe modulation doped heterostructure grown by LEPECVD. A forward-to-reverse current ratio of more than 104 was obtained.

Fig. 4. Gate-controlled rectifier. (a) Potential distribution along the gate and potential induced by the gate inside the semiconductor. (b) SEM image of the nanofabricated diode. The Ge has been etched faster than the surrounding Si0.3Ge0.7, so the location of the Ge quantum well (QW) can be identified by a dark narrow slit 83 nm below the top surface.

Nanopatterning of semiconductor substrates

The templates for pre-patterning of Si substrates for subsequent quantum dot growth by LEPECVD were developed and successfully tested both in PMMA and by a lift-off process. These patterns consist of dots or perpendicular lines which will be transferred to the substrate as pits or trenches after reactive ion etching. The patterns will be transferred to the substrates together with the alignment marks for the second-level patterning of metal electrodes. It is planned to address individual quantum dots and realize single-electron and resonant tunneling transistors.

Facilities

Electron beam lithography

The ever-growing demand for increasing the integration scale of digital electronics has prompted a search for novel devices and fabrication techniques at the nanometer scale. State of the art 45 nm optical lithography (Intel, 2008) is able to deliver transistors with the gate length as small as 35 nm. Electron beam lithography (EBL) is an indispensable technique for making the nanoelectronic devices on an even smaller scale (Fig. 5).

Fig. 5. The narrowest line that can be patterned by our EBL system is ~ 11 nm wide. The line consists of 3 nm of chromium and 10 nm of gold. The line was patterned on a standard SiO2/Si substrate.

In this technique, a highly focused electron beam is scanned over a surface covered by a resist sensitive to electron radiation (e.g., polymethyl-methacrylate - PMMA). Exposed areas become more (positive resist) or less (negative resist) soluble in organic solvents (e.g., methyl isobutyl ketone - MIBK), which are used to develop the exposed pattern. The pattern is transferred to the substrate by etching (e.g., reactive ion etching) or lift-off (e.g., metallization).

While the resolution of optical lithography is mostly limited by the wavelength of the excimer laser, diffraction is not the limiting factor in EBL due to a very small electron wavelength (less than 0.01 nm at 20 keV). The resolution of EBL is mostly limited by imperfections in the electron optics (aberrations limit the minimum electron beam spot size to ~ 2 nm) and electron backscattering from the substrate. These effects limit the smallest feature size to ~ 10 nm.

EBL is not suitable for a large scale production because electron beam exposure is a serial process (i.e., it is much slower than optical lithography). On the other hand, EBL is a fabrication tool of choice in nanoelectronics and low-dimensional physics. It allows researchers to fabricate and investigate very small devices which might be used in the future. EBL is used industrially in mask making for optical and x-ray lithography.

The work on EBL in Como started in May 2005 with the installation of the scanning electron microscope (SEM). The group is equipped with a Philips XL30 SFEG SEM with a Raith Elphy Quantum lithography attachment and a Scanservice beam blanker. This system (shown in Fig. 6) is used to pattern graphene and semiconductor heterostructures.

Fig. 6. Our EBL system. Parts: 1. Column 2. Specimen chamber 3. Secondary electron detector 4. Scanservice final aperture with integrated beam blanker 5. CCD camera 6. High tension valve 7. Liquid N2 tank (for X-ray detector) 8. Keithley pico-ammeter (to measure beam current) 9. Beam blanker power supply 10. Vacuum pumps and high tension circuitry 11. Electronics (printed circuits boards) 12. Power supply 13. Lithography PC (Raith Elphy Quantum) 14. SEM PC with integrated X-ray analyzer

Optical lithography

The group is equipped with a Karl Suss MA56 mask aligner (contact and proximity printing, 4” wafers, 5” masks, i-line, 20 mWcm-2). The aligner is used to pattern SiGe heterostructures (mostly into Hall bars on which nanostructures are overlaid by EBL).

Atomic force microscopy

The group is equipped with a Veeco Innova atomic force microscope. The microscope is used to scan graphene devices and quantum dots grown on pre-patterned Si substrates.

He cryostat

The group is equipped with a Cryogenic cryogen free (i.e., a closed cycle liquid helium-4) magnet system to 7.5 T with an integrated variable temperature insert. The lowest temperature which can be reached by this cryostat is about 1.4 K. The cryostat is connected to a transport measurement system comprised of digital source meters, multi meters, preamplifiers, function generators, an oscilloscope, and an acquisition board. This system is used for the characterization of fabricated nanodevices.

Clean room

We have a class ~ 100 clean room in which all device processing is done. The clean room is equipped with ovens, spin-coaters, wet benches, ultrasonic baths, a plasma asher, and an optical microscope. A mask aligner is also inside the clean room.

Publications (Journals)

  1. L. G. Rizzi, M. Bianchi, A. Behnam, E. Carrion, E. Guerriero, L. Polloni, E. Pop, and R. Sordan: Cascading wafer-scale integrated graphene complementary inverters under ambient conditions, Nano Lett. 12, 3948 (2012).
  2. M. Aouassa, I. Berbezier, L. Favre, A. Ronda, M. Bollani, R. Sordan, A. Delobbe, and P. Sudraud: Design of free patterns of nanocrystals with ad hoc features via templated dewetting, Appl. Phys. Lett. 101, 013117 (2012).
  3. D. Chrastina, G. M. Vanacore, M. Bollani, P. Boye, S. Schöder, M. Burghammer, R. Sordan, G. Isella, M. Zani, and A. Tagliaferri: Patterning-induced strain relief in single lithographic SiGe nanostructures studied by nanobeam x-ray diffraction, Nanotechnology 23, 155702 (2012).
  4. E. Guerriero, L. Polloni, L. G. Rizzi, M. Bianchi, G. Mondello, and R. Sordan: Graphene audio voltage amplifier, Small 8, 357 (2012).
  5. M. Bollani, D. Chrastina, V. Montuori, D. Terziotti, E. Bonera, G. M. Vanacore, A. Tagliaferri, R. Sordan, C. Spinella, and G. Nicotra: Homogeneity of Ge-rich nanostructures as characterized by chemical etching and transmission electron microscopy, Nanotechnology 23, 045302 (2012).
  6. A. Sagar, K. Balasubramanian, M. Burghard, K. Kern, and R. Sordan: Polymer-electrolyte gated graphene transistors for analog and digital phase detection, Appl. Phys. Lett. 99, 043307 (2011).
  7. E. U. Stützel, M. Burghard, K. Kern, F. Traversi, F. Nichele, and R. Sordan: A graphene nanoribbon memory cell, Small 6, 2822 (2010).
  8. M. Bollani, D. Chrastina, A. Fedorov, R. Sordan, A. Picco, and E. Bonera: Ge-rich islands grown on patterned Si substrates by low-energy plasma-enhanced chemical vapour deposition, Nanotechnology 21, 475302 (2010).
  9. G. M. Vanacore, M. Zani, G. Isella, J. Osmond, M. Bollani, and A. Tagliaferri: Quantitative investigation of the influence of carbon surfactant on Ge surface diffusion and island nucleation on Si(100), Phys. Rev. B 82, 125456 (2010).
  10. M. Bollani, E. Bonera, D. Chrastina, A. Fedorov, V. Montuori, A. Picco, A. Tagliaferri, G. Vanacore, and R. Sordan: Ordered arrays of SiGe islands from low-energy PECVD, Nanoscale Res. Lett. 5, 1917 (2010).
  11. G. M. Vanacore, M. Zani, M. Bollani, D. Colombo, G. Isella, J. Osmond, R. Sordan and, A. Tagliaferri: Size evolution of ordered SiGe islands grown by surface thermal diffusion on pit-patterned Si(100) surface, Nanoscale Res. Lett. 5, 1921 (2010).
  12. F. Traversi, F. J. Guzman-Vazquez, L. G. Rizzi, V. Russo, C. S. Casari, C. Gómez-Navarro, and R. Sordan: Elastic properties of graphene suspended on a polymer substrate by e-beam exposure, New J. Phys. 12, 023034 (2010).
  13. V. Kapaklis, S. Grammatikopoulos, R. Sordan, A. Miranda, F. Traversi, H. von Känel, D. Trachylis, P. Poulopoulos, and C. Politis: Nanolithographic templates using diblock copolymer films on chemically heterogeneous substrates, J. Nanosci. Nanotechnol. 10, 6056 (2010).
  14. F. Traversi, V. Russo, and R. Sordan: Integrated complementary graphene inverter, Appl. Phys. Lett. 94, 223312 (2009).
  15. R. Sordan, A. Miranda, F. Traversi, D. Colombo, D. Chrastina, G. Isella, M. Masserini, L. Miglio, K. Kern, and K. Balasubramanian: Vertical arrays of nanofluidic channels fabricated without nanolithography, Lab Chip 9, 1556 (2009).
  16. R. Sordan, F. Traversi, and V. Russo: Logic gates with a single graphene transistor, Appl. Phys. Lett. 94, 073305 (2009).
  17. R. Sordan, A. Miranda, J. Osmond, D. Colombo, D. Chrastina, G. Isella, and H. von Känel: Gate-controlled rectifying barrier in a two-dimensional hole gas, Nanotechnology 19, 335201 (2008).
  18. R. Sordan, A. Miranda, J. Osmond, D. Chrastina, G. Isella, and H. von Känel: Logic gates with a single Hall bar heterostructure, Appl. Phys. Lett. 89, 152122 (2006).

Graphene software - SVGMarks

Intro

Graphene devices are usually fabricated by patterning graphene deposited on a Si substrate by mechanical exfoliation. Such deposited graphene flakes are randomly distributed on a chip. The probability of obtaining monolayer graphene in this process is very small (about 1 monolayer per 3 mm2). For this reason, patterning graphene (or any other sparse and randomly distributed set of objects) requires deposition of graphene on a prepatterned substrate containing a coordinate system (usually defined by a matrix of marks). The coordinate system is used to precisely locate graphene on a chip allowing design of lithographic patterns. The software presented here (SVGMarks) is used to process images of graphene flakes and marks such that they can be imported into a design file.

Image processing is necessary for two reasons. Firstly, the coordinate system of the image usually does not coincide with the coordinate system of the design file (even if images are taken with great care a slight rotation is always present). Secondly, the exact image dimensions and coordinates of the image center are required to scale and place an image in the correct position in the design file.

Download

SVGMarks is free to use and distribute.

Requirements

  1. .NET Framework (free).
    Newer Windows PCs already have .NET Framework installed. To find out do you need it just run SVGMarks. If you do not get any error you are fine.
  2. Inkscape (free).
    SVGMarks uses Inkscape for manual alignment.

Installation

  1. Unzip SVGMarks.zip in the folder of your choice. The zip file contains two files: SVGMarks.exe (executable) and SVGMarks.ini (configuration file; SVGMarks does not mess with the Windows registry).
  2. Open SVGMarks.ini in a text editor (e.g. Notepad) and edit the variable [Inkscape] if necessary. This variable represents the full file name (including path) of the Inkscape executable which you should have already installed. The current value C:\Program Files\Inkscape\inkscape.exe corresponds to an executable in an English Windows installation. Edit the variable to match the executable on your PC.
  3. Optional: if you like SVGMarks make a shortcut to SVGMarks.exe on the desktop.

Manual

  1. Run SVGMarks.exe. The window shown in Fig. 7 appears.

    Fig. 7. SVGMarks window. The text box in the upper left corner (‘Input image’) contains the file name of the image to be processed. Initially, the program offers image.jpg stored in your personal folder (as an example - this image probably does not exist on your PC). Other text boxes contain names of the files which will be created by SVGMarks during processing (their names are derived from the file name of the input image).

  2. Click ‘Open’ and browse for the image to be processed. Selected image will be shown in the Preview pane on the right (Fig. 8).

    If you prefer you can type the full file name in the text box instead of browsing for the image. If you decide to type, press Enter when you finish to tell the program that your input is over and that you want to open the image.

    Fig. 8. Preview of the image to be processed. The image shows graphene flakes of different thicknesses (from a monolayer to a thick multilayer). Three Au marks (which define the local coordinate system of the image) can also be seen. In this image the sample is deliberately rotated in order to demonstrate the capabilities of SVGMarks. In reality, the axes of the local coordinate system should be as parallel to the image edges as possible (i.e., the line connecting the two bottommost marks should be as parallel to the horizontal edge of the image as possible).

  3. Click ‘Align’ and wait until Inkscape shows up (Fig. 9).

    Fig. 9. The input image loaded in Inkscape with two black marks. The mark in the bottom left corner is the origin (labeled by ‘Mark O’ in the text box ‘Origin’) and the mark in the bottom right corner defines a point along the x-axis (labeled by ‘Mark X’ in the text box ‘Point along x-axis’).

  4. Place the black marks over the corresponding marks in the image (Fig. 10).

    Fig. 10. Placing black Inkscape marks over the marks in the image: (Top) Roughly place the marks and click on one of the marks (to select it). (Bottom) Click on button ‘Zoom to fit selection in window’ located in the Inkscape toolbar and make a fine adjustment of the mark position. When finished click on button ‘Zoom to fit drawing in window’ (to go to the previous view). Repeat the procedure for the other mark.

  5. Close Inkscape (save document).
  6. Type the coordinates of the marks in the text boxes ‘X’ and ‘Y’ (values and units should correspond to the design file).

    In this case the coordinates are (Mark O) x = 400 µm, y = -400 µm and (Mark X) x = 480 µm. (Fig. 11)

    Fig. 11. Coordinates of the local origin and point along the x-axis in the design file (where the processed image will be placed).

  7. Click Rotate.

    After processing is done the rotated image appears in the preview pane (Fig. 12). This image is stored both in PNG and BMP format (file names are in the text boxes ‘Output - Rotated PNG’ and ‘Output - Rotated BMP’).

    Fig. 12. The rotated image can be imported into the design file as the axes of its local coordinate system are parallel to the axes of the coordinate system of the design file (after rotation, translational symmetry is established between the systems).

    The coordinates of the image center and image dimensions are shown in the bottommost text boxes (Fig. 13). These data are used to correctly place the image in the design file.

    Fig. 13. Numerical values which define the position of the rotated image in the design file. Angle (in degrees) is not used in the design file (it just shows how much the original image was rotated).

    The rest of this manual explains how to place the rotated image in the design file (keep SVGMarks open). In this case the Raith Elphy software suite is used.

  8. Open design file in Elphy (Fig. 14).

    Fig. 14. Design file opened in Elphy (left window) and rotated image (right window).

  9. Open the rotated BMP image: File → Open image... → Files of type: Bitmap files (*.bmp) → Browse for the rotated image whose full file name is given in the SVGMarks text box ‘Output - Rotated BMP’. Hint: Click in the text box ‘Output - Rotated BMP’ → Ctrl+A (to select all; works in English Windows) → Ctrl+C (to copy the full file name) → Paste in File name. The image shows up (Fig. 14).
  10. Open image information window: Edit → Image information... (Fig. 15) and enter the data shown in Fig. 13.

    Fig. 15. Coordinates of the image center and image dimensions. Copy/Paste this data from SVGMarks (Fig. 13).

  11. Click on the design file window to put it in the foreground. Click Options → Show video. The rotated image shows up in the design file (Fig. 16).

    Fig. 16. Rotated image placed in the correct position in the design file. (Top) Overview. (Bottom) Magnified parts of the design file around marks demonstrate fine alignment.

  12. Design your pattern...

Linux version

Coming soon...

Copyright © 2010 L-NESS Como

Last updated: 14th May 2013